Dedicated neural processing units built for convolution operations struggle to justify their silicon real estate in modern transformer architectures. When Apple introduced the Neural Engine in the A11 chip, the execution datapath prioritized dense, predictable tensor reductions optimized for convolutional vision models.
Reverse-engineering the M1 hardware scheduler and memory interfaces highlights why fixed-function accelerators hit a wall. The engine relies on rigid, static compile-time scheduling and specialized local memory banks that cannot adapt efficiently to the dynamic memory access and autoregressive decoding patterns demanded by large language models.
General-purpose GPU compute engines absorbed these workloads because modern model inference requires flexible memory bandwidth and programmable vector units rather than rigid application-specific datapaths. As unified memory bandwidth scaled past eight hundred gigabytes per second on modern chips, isolated accelerators lost their performance advantage over tightly integrated shader cores.
Fixed-function accelerators inevitably lose when software primitives evolve faster than hardware fabrication cycles.
